The traditional approach to moving scan test data from chip-level pins to core-level scan channels is under pressure due to the dramatic rise in design size, design complexity, and test adaptation. To ...

For decades, process and design scaling has triggered the adoption of transformative test solutions. About twenty years ago, when at-speed test became a de-facto requirement, on-chip compression ...

Companies specializing in circuit board and system design-for-test (DFT) tools are pursuing a variety of strategies to serve test and debug applications based on innovations they announced over the ...

Despite its standardization as IEEE 1149.1 in 1990 and wide use in the industry, many test engineers and developers still do not fully understand the benefits of boundary scan test. The misconceptions ...